1. Field of the Invention
The present invention relates to a microcomputer, a program development apparatus for the microcomputer, and a program development system, particularly to the development of programs for Application Specific Integrated Circuits (ASIC).
2. Description of the Prior Art
Recently, demand has grown for development of Large Scale Integrated (LSI) circuits including microcomputer for specific application as electronic equipment is provided with more advanced functions, is further compacted, and becomes less expensive. It is also indispensable to develop a program for each developed LSI.
FIG. 33 is a schematic showing a program development procedure and a program development apparatus for the existing microcomputer (hereafter referred to as MCU).
A program for a MCU to be mounted on the evaluation board 4 is developed by using the program development apparatus 100. The evaluation board 4 is a board which will be operated by an MCU to be operated by a developed program. The program development apparatus 100 includes a host computer 1 for program development, a debugger 2, and a pod 3. A microcomputer 32 for program evaluation (hereafter referred to as evaluation MCU) equivalent to the MCU to be mounted. on the evaluation board 4 is mounted. on the pod 3. The pod 3 connects with a connector 40 which is connected to a socket 41 on the evaluation board 4 where the MCU is to be mounted. The program development apparatus 100 is manufactured by corresponding to the internal constitution of the MCU to be mounted on the evaluation board 4.
The program development apparatus 100 gives a program or data to the evaluation MCU 33 instead of the internal memory or external memory of the MCU to be mounted on the evaluation board 4 in order to operate the evaluation MCU 32 and traces the signal of each terminal in order to debug the program. The program development apparatus 100 also gives a signal same as the signal under actual operation of the MCU to the evaluation board 4 through the connector 40.
The host computer 1 gives various instructions to the debugger 2 for program development. The debugger 2 controls the operation of the evaluation MCU 32, holds the result of tracing the signal, and controls the pod 3 in accordance with the instructions from the host computer 1. The pod 3 controls exchange of signals between the evaluation MCU 32 and debugger 2 or evaluation board 4 by responding to the address signal outputted from the evaluation MCU 32, various control signals, and control signal given from the debugger 2.
A program developed by the development apparatus 100 is written in a EPROM (Electrically Programmable Read Only Memory) 5. A mask for ROM (Read Only Memory) is made by using the EPROM 5 and the program is written in the ROM 70 in the MCU 7 by using the mask 5.
FIG. 34 shows an approximate constitution of the debugger 2. The debugger 2 includes a control CPU (Central Processing Unit) 21, program memory 22, tracing control circuit 23, break control circuit 24, interface 25, and evaluation MCU control circuit 26. The program memory 22 stores the program for operating the control CPU 21, which is also used to run a developed program when the program is debugged. The control CPU 21 controls each control circuit in the debugger 2. The tracing control circuit 23 performs tracing control after running the program. The break control circuit 24 performs break control. The evaluation MCU control circuit 26 controls the evaluation MCU in the pod 3. The address signal given from the pod 3 is given to the control CPU 21, tracing control circuit 23, break control circuit 24, and evaluation MCU control circuit 26 through the address latch 27. Data is transferred between the control CPU 21 or program memory 22 and the pod 3 through the data bus buffer 28.
FIG. 35 shows an approximate constitution of the pod 3. The pod 3 includes a port emulation circuit 31, evaluation MCU 32, address latch 33, and data bus buffer 34. The port emulation circuit 31 gives data and address signal same as those under actual operation of the MCU to the evaluation board 4 through the data bus DB1 by means of time-sharing. The evaluation MCU 32 gives an address signal to the port emulation circuit 31 and address latch 33 through the address bus AB1.
Data is transferred between the evaluation MCU 32 and the port emulation circuit 31 or data bus buffer 34 through the data bus DB2. Some signal lines of the data bus DB2 are used. to transfer data and address signal by means of time-sharing. Input and output signals in the MCU other than those which should pass through the port emulation circuit 31 are transferred between the evaluation MCU 32 and evaluation board 4 through the signal line DB3.
FIG. 36 shows the constitution of the main portion of the port emulation circuit 31 in detail. The port emulation circuit 31 includes an address detection circuit 310 and input/output control circuit 311, and a plurality of input/output circuits. FIG. 36 shows only one input/output circuit 312 related. to a set of input/output terminals TP1 and TP2. The input/output terminal TP1 is connected to the evaluation MCU 32 and the input/output terminal TP2 is connected to the evaluation board 4 or debugger 2.
The input/output circuit 312 includes buffers BF1 and BF2, latches LT1 and LT2, transfer gates G1 and G2, and inverters G3 and G4. The address detection circuit 310 detects a predetermined address by responding to the address signal AD given from the evaluation MCU 32 and gives a detection signal to the input/output control circuit 311. That is, the address detection circuit 310 judges whether the the address signal AD given from the evaluation MCU 32 specifies the internal address area of the MCU 32 or the external address area of it and generates a detection signal in accordance with the result of judgment.
The input/output circuit 311 gives control signals CN1 to CN4 to the input/output circuit 312 by responding to the data enable signal /E and read/write signal R/W given from the evaluation MCU 32 and the detection signal given from the address detection circuit 310. Thereby, the input/output circuit 312 is set to the input or output state and an input/output operation timing is determined.
Addresses detected by the address detection circuit 310 are in the chip-inside address area of the MCU 32, which are normally set by hardware assembled in the address detection circuit 310. Because of space saving, the input/output control circuit 311 and address detection circuit 310 frequently comprise a one-chip IC in recent years.
The data enable signal/E indicates the data input/output enabling state for "L" and the data input/output disabling state for "H". The read/write signal R/W indicates the read state for "H" and the write state for "L".
When the control signal CN1 goes "L" and control signal CN2 goes "H", the buffer BF1 turns on and the buffer BF2 turns off. Thereby, the input/output circuit 312 is set to the output state. As a result, the control signal CN3 goes "L". Therefore, a signal (data or address signal) given from the evaluation MCU 32 to the input/output terminal TP1 is outputted to the input/output terminal TP2 through the latch LT1 and buffer BF1.
When the control signal CN1 goes "H" and the control signal CN2 goes "L", the buffer BF1 turns off and the buffer BF2 turns on. Thereby, the input/output circuit 312 is set to the input state. As a result, the control signal CN4 goes "L". Therefore, a signal given from the evaluation board 4 to the input/output terminal TP2 is inputted to the input/output terminal TP1 through the buffer BF2, latch LT2, and transfer gate G2.
The input/output terminal TP1 performs the function equivalent to one input/output terminal of the MCU. When a program is debugged, however, input/output terminals of the evaluation MCU 32 perform the operation for debugging such as outputting of normal operating signal and debugging signal by means of time-sharing. Therefore, the operation timing is controlled and the input/output state is set by the input/output control circuit 311 of the port emulation circuit 31 so that the operation of the input/output terminal TP1 will be apparently equivalent to the normal operation of the MCU.
FIG. 37 shows the constitution of a general MCU. The MCU 32 includes a CPU 321, RAM 322, ROM 323, and peripheral circuit section 324. The peripheral circuit section 324 includes a timer 325 and input/output port 326.
FIG. 38 shows a developed MCU. In the MCU 32, the CPU 321, RAM 322, ROM 323, timer 325, and input/output port 326 are connected to the bus EB for transferring signals. The bus EB, CPU 321, timer 325, and input/output port 326 are connected to a peripheral terminal circuit 327 for exchanging signals between the outside and inside of a chip.
The bus EB, timer 325, input/output port 326, and peripheral terminal circuit 327 correspond to the peripheral circuit section 324 shown in FIG. 37.
FIG. 39 shows another MCU. The CPU 321, RAM 322, ROM 323, A-D converter 328, and UART (Universal Asynchronous Receiver Transmitter) 329 are connected to the bus EB for transferring signals. The bus EB, CPU 321, A-D converter 328, and UART 329 are connected to an input/output circuit 330 for exchanging signals between the outside and inside of a chip. Therefore, signals can directly be exchanged between the CPU 321 and input/output circuit 330, between the A-D converter 328 and input/output circuit 330, and between the UART 329 and input/output circuit 330.
The bus EB, A-D converter 328, UART 329, and input/output circuit 330 correspond to the peripheral circuit section 324 shown in FIG. 37.
FIG. 40 shows an address map of the MCU 32. The address space in FIG. 40 is divided into the chip-inside address area A and chip-outside address area B. The chip-inside address area A includes the SFR (Special Function Register) area al assigned to control/data registers such as the timer 325 and input/output port 326 of the peripheral circuit section 324 in the MCU 32, the stored RAM area a2 assigned to the RAM 322 in the MCU 32, and the stored ROM area a3 assigned to the ROM 323 in the MCU 32.
When the evaluation MCU 32 in the program development apparatus 100 outputs an address signal for specifying an address in the SFR area a1, stored RAM area a2, or stored ROM area a3; the input/output control circuit 311 shown in FIG. 36 sets the input/output circuit 312 to the output state so that the signal outputted from the evaluation board 4 (or debugger 2) will not be given to the input/output terminals of the evaluation MCU 32. When the evaluation MCU 32 outputs an address signal for specifying an address in the extended section b, the input/output control circuit 311 sets the input/output circuit 312 to the input state so that the signal outputted from the evaluation board 4 (or debugger 2) will be given to the input/output terminals of the evaluation MCU 32.
An ASIC using an MCU as a core is recently developed in order to make applied equipment intelligent. To quickly develop the ASIC in a short time, new MCUs are frequently developed by using an already developed MCU as a core.
FIG. 41 shows the schematic constitution of the above new MCUs. The MCU 32a includes a MCU core 32b and a newly-added circuit section 32c in the same chip. The MCU core 32b includes a CPU 321, RAM 322, ROM 323, and peripheral circuit section 324 similarly to the already developed MCU 32 shown in FIG. 37.
FIG. 42 shows a new MCU. The MCU 32a includes a MCU core 32b and peripheral terminal circuit 327 having the same constitution as the MCU 32 shown in FIG. 38, and further includes a newly-added circuit section 32c for realizing a specific function.
FIG. 43 shows the constitution of the main portion and signal lines of the MCU 32a shown in FIGS. 41 and 42. Address signals and data are exchanged. between the MCU core 32b and input/output circuit 16 through the signal line L1. The MCU core 32b outputs the latch signal ALE to the newly-added circuit section 32c and outside of the chip through the signal line L2 and outputs the data enable signal/E and read/write signal R/W to the newly-added circuit section 32c and outside of the chip through the signal lines L3 and L4. Signals are exchanged between the newly-added circuit section 32c and input/output circuit 16 through the signal line L5.
An operating-mode determination circuit 17 gives the operating-mode signal S14 to the MCU core 32b by responding to the signal given from an external unit. The operating-mode signal S14 is also given to the newly-added circuit section 32c according to necessity. When the operating mode signal S14 goes "L", the MCU 32a is set to the normal operating mode. When the operating-mode signal S14 goes "H", the MCU 32a is set to the operating mode at development of a program.
FIG. 44 shows the constitution of an input/output circuit 16. The input/output circuit 16 includes a selection circuit 161, buffer 162, and external terminal 163.
The selection circuit 161 receives the MCU output signal DOM and newly-added circuit section output signal DOR and controls the buffer 162 by responding to the MCU control signal CM and newly-added circuit section control signal CR. The buffer 162 outputs the MCU output signal DOM or newly-added circuit section output signal DOR of the outside of the chip through the external terminal 163 and gives the signal to the inside of the chip as the MCU input signal DIM or newly-added circuit section input signal DIR.
The MCU control signal CM, MCU output signal DOM, and MCU input signal DIM are exchanged between the MCU core 32b and input/output circuit 16 through the signal line L1. The newly-added circuit section control signal CR, newly-added circuit section output signal DOR, and newly-added circuit section input signal DIR are exchanged between the newly-added circuit section 32c and input/output circuit 16 through the signal line L5.
FIG. 45 is a timing chart showing the operation when the MCU core 32b reads data from the newly-added circuit section 32c in the MCU 32a.
In the read period TR, the MCU core 32b is set to the read state and the read/write signal R/W is set to "H". Under this state, the MCU core 32b provides the input/output circuit 16 with the address signal AD1 for specifying the newly-added circuit section 32c through the signal line L1. Then, the address signal AD1 is given to the newly-added circuit section 32c from the input/output circuit 16 through the signal line L5.
Then, the address signal AD1 is fetched to the newly-added circuit section 32c by using the change of the latch signal ALE to "H" as a trigger. Thereby, the newly-added circuit section 32c provides the input/output circuit 16 with the data DT1 corresponding to the address signal AD1 through the signal line L5 from the point of time the data enable signal/E outputted from the MCU core 32b goes active ("L").
Moreover, the data DT1 is given to the MCU core 32b from the input/output circuit 16 through the signal line L1. Thus, data is read from the newly-added circuit section 32c.
FIG. 46 shows an address map of the MCU 32a in FIG. 41. Because the chip-inside address area A does not have an address area to be assigned to the memory and register of the newly-added circuit section 32c, the newly-added circuit area "c" to be assigned to the newly-added circuit section 32c is formed in the new chip-inside address area C1 corresponding to part of the chip-outside address area B shown in FIG. 40. Remaining area of address space is used as the chip-outside address area B1 containing the extended section b1.
Therefore, though the newly-added circuit section 32c shown in FIG. 41 is formed on the chip "ch" shared with the MCU core 32b, it is assigned with the the new chip-inside address area Cl other than the chip-inside address area A. The memory and register arranged in the newly-added circuit section 32c is specified by the addresses in the new chip-inside address area C.